The present invention relates to memory, and is more particularly related to a memory structure and method of making.
Memory structures can have multiple layers and can require a transistor to decode the memory. The fabrication of memory structures of this type can require a significant number of processing steps for each layer of memory. Short processing time in the clean room environment is desirable because operation and maintenance of the clean room environment for memory cell fabrication using semiconductor technology processes is time consuming and expensive. Fewer process steps in memory structure fabrication are desirable because each fabrication process step is both an expense and an opportunity to reduce yield. As such, it would be an advance in the art to reduce the time and processing required to fabricate memory structures.
Layered memory structures can be fabricated on a semiconductor wafer that can be diced into a plurality of semiconductor chips. In large scale integration, a goal is to maximize the number of devices on a semiconductor chip. When a memory structure requires a transistor for decoding, the goal of large-scale integration in mitigated by the requirement for the space that is taken up by the decoding transistor. As such, it would be an advance in the art to fabricate memory structures without decoding transistors.
In one embodiment, a memory structure has a plurality of row conductors intersecting a plurality of column conductors at a plurality of intersections. Each intersection includes an electrically linear resistive element in series with a voltage breakdown element.
These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.